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Regulation: R23 Branch: Electrical and Electronics Engineering Semester: 3-1

Digital Circuits

Verified vs. official syllabus Checked 2026-07-01

Both the subject list and detailed unit topics are sourced from an autonomous JNTUK-affiliated college's published syllabus and have not been independently cross-confirmed against JNTUK's own exam records -- autonomous colleges may adapt content locally.

Unit-wise syllabus

UNIT 01

Combinational Logic Circuits - I

Combinational logic definition, canonical forms, switching equations from truth tables; Simplification using Boolean theorems, NAND/NOR implementations, Karnaugh maps (3, 4, 5 variables), don't-care terms; Simplifying max-term equations, Quine-McCluskey minimization technique, general approach to combinational logic design; Look-ahead carry adder, cascading full adders, 4-bit adder-subtractor, BCD adder, Excess-3 adder, binary comparators

UNIT 02

Combinational Logic Circuits - II

Decoders, BCD decoders, 7-segment decoder, higher-order decoders; Multiplexers, higher-order multiplexing, de-multiplexers; realization of Boolean functions using decoders and multiplexers; Encoders, priority encoder; ROM and R/W memories, PROM, PAL, PLA basic structures, programming tables, realization of Boolean functions

UNIT 03

Sequential Logic Circuits

Flip-flop timing considerations, master-slave and edge-triggered flip-flops, characteristic equations; Flip-flops with reset and clear terminals, excitation tables, flip-flop conversion; Design of asynchronous and synchronous counters, modulus-N counters, Johnson counter, ring counter; Registers: buffer, control buffer, shift, bidirectional shift and universal shift registers

UNIT 04

Sequential Circuit Design

Mealy and Moore models, state machine notation; Synchronous sequential circuit analysis, construction of state diagrams; Analysis of clocked sequential circuits, realization of a sequence detector circuit; State reduction and assignments, design procedure

UNIT 05

Digital Integrated Circuits

Logic levels, propagation delay time, power dissipation, fan-out and fan-in, noise margin; Logic families: RTL and DTL circuits, TTL; Emitter-coupled logic (ECL), metal-oxide semiconductor (MOS); Complementary MOS (CMOS), CMOS transmission gate circuits